EPM7128ELC84-10 vs EPM7128ELC84-12 Comparación
Comparación detallada lado a lado de EPM7128ELC84-10 por Intel y EPM7128ELC84-12 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7128ELC84-10 | EPM7128ELC84-12 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $7,20 | $10,40 |
| Family | MAX 7000 | MAX 7000 (MAX 7000E series) |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | 128 |
| Equivalent Logic Gates | [DATA_NEEDED: equivalent gate count from datasheet] | — |
| User I/Os | 68 | 84 |
| Dedicated Inputs | 12 | — |
| Operating Voltage (VCCINT/VCClO) | 5 V | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Counter Frequency (fCNT) | [DATA_NEEDED: fCNT from datasheet] | — |
| Encapsulado | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-Lead, QCCJ) |
| Tipo de montaje | Surface Mount / Socket | Surface Mount (PLCC socket compatible) |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Technology | EEPROM-based CMOS | — |
| Programming Interface | IEEE 1149.1 (JTAG) ISP | JTAG (IEEE 1149.1) / ISP |
| In-System Programmable | Yes | — |
| Estado RoHS | [DATA_NEEDED: RoHS status from datasheet] | Non-compliant (legacy 5V part, SnPb finish) |
| Lead-Free | [DATA_NEEDED: lead-free status from datasheet] | — |
| Logic Family | — | CMOS, EEPROM-based |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tpd1) | — | 12 ns |
| Internal Global Clock Frequency | — | 90.9 MHz |
| Setup Time | — | 4.5 ns |
| Supply Voltage (VCCINT / VCCIO) | — | 5 V (4.75 V to 5.25 V) |
| Recuento de pines | — | 84 |