EPM7128ELC84-12 vs EPM7128ELC84-20 Comparación
Comparación detallada lado a lado de EPM7128ELC84-12 por Altera y EPM7128ELC84-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7128ELC84-12 | EPM7128ELC84-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,40 | $24,20 |
| Family | MAX 7000 (MAX 7000E series) | — |
| Logic Family | CMOS, EEPROM-based | — |
| Usable Gates | 2,500 | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| User I/Os | 84 | — |
| Propagation Delay (tpd1) | 12 ns | — |
| Internal Global Clock Frequency | 90.9 MHz | — |
| Setup Time | 4.5 ns | — |
| Supply Voltage (VCCINT / VCCIO) | 5 V (4.75 V to 5.25 V) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Encapsulado | 84-pin PLCC (J-Lead, QCCJ) | — |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| Recuento de pines | 84 | — |
| Estado RoHS | Non-compliant (legacy 5V part, SnPb finish) | Contains lead (pre-RoHS, SnPb finish) |
| Series | — | MAX 7000 |
| Device Family | — | EPM7128 (CPLD) |
| Number of Macrocells | — | 128 |
| Number of Usable Gates | — | 2500 |
| Number of User I/Os | — | 68 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (fCNT) | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Supply Voltage Tolerance | — | 4.75 V to 5.25 V |
| Technology | — | CMOS, EEPROM-based (non-volatile) |
| Programmable Interface | — | IEEE Std. 1149.1 (JTAG) |
| Package Type | — | PLCC-84 (J-Lead, J-bend) |