EPM7128SLC84-15 vs EPM7128SLC84-10 Comparación
Comparación detallada lado a lado de EPM7128SLC84-15 por Intel y EPM7128SLC84-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7128SLC84-15 - 128-Macrocell MAX 7000S CPLD, 84-PLCC | Intel / Altera
EPM7128SLC84-15 ⚠ Última compraComparación de especificaciones
| Parámetro | EPM7128SLC84-15 | EPM7128SLC84-10 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,40 | $9,75 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | — |
| User I/Os | 68 (in 84-PLCC) | 68 |
| Encapsulado | 84-Pin PLCC (J-Lead, J84) | PLCC-84 (J-lead) |
| Speed Grade | -15 (15 ns pin-to-pin delay) | — |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Internal Frequency (fMAX) | 76.9 MHz | — |
| Logic Family / Process | CMOS, 5V, EEPROM | — |
| Supply Voltage (VCCINT) | 5 V | 5 V |
| I/O Standard Support | 5.0 V TTL/CMOS (multi-volt I/O compatible with 3.3V) | — |
| Programming Interface | JTAG (IEEE Std. 1149.1), in-system programmable | — |
| Configuration Memory | Non-volatile EEPROM (instant-on, no boot PROM) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Estado RoHS | Non-RoHS (legacy 5V part) | Non-compliant (contains lead in PLCC) |
| Tipo de montaje | Surface Mount / Socketed (PLCC-84 socket) | Surface Mount (J-bend) |
| Logic Gates | — | 2500 |
| Total Package Pins | — | 84 |
| Propagation Delay (tpd) | — | 10 ns |
| Maximum Operating Frequency | — | 125 MHz |
| Internal Frequency | — | 250 MHz |
| MultiVolt I/O Support | — | 2.5 V / 3.3 V / 5 V |
| Program Memory Type | — | EEPROM (in-system programmable) |
| JTAG (IEEE 1149.1) | — | Yes |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |