EPM7128SLI84-10N vs EPM7128SLC84-6N Comparación
Comparación detallada lado a lado de EPM7128SLI84-10N por Altera y EPM7128SLC84-6N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndIntel
EPM7128SLC84-6N - MAX 7000S CPLD, 128 Macro, 6ns, 84-PLCC | Intel
EPM7128SLC84-6N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM7128SLI84-10N | EPM7128SLC84-6N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,45 | $8,75 |
| Family | MAX 7000S | MAX 7000S |
| Logic Cells / Macro Cells | 128 macro cells | — |
| Usable Gates | 2,500 | — |
| Number of Logic Elements / Blocks | 16 Logic Array Blocks (LABs) | — |
| User I/Os | 68 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | 125 MHz | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V typical) | — |
| I/O Voltage Tolerance | 3.3 V / 5 V MultiVolt I/O | — |
| Process Technology | CMOS EEPROM | CMOS, EEPROM |
| Programmability | In-system programmable (ISP), non-volatile EEPROM | — |
| Boundary-Scan (JTAG) | IEEE Std 1149.1 compliant | — |
| Encapsulado | 84-pin PLCC (J-Lead) | 84-pin PLCC (J-lead) |
| Tipo de montaje | Surface Mount | — |
| Temperatura de funcionamiento | -40 C to +85 C (Industrial) | [DATA_NEEDED: operating temperature range] |
| Estado RoHS | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] | Non-Compliant (legacy 5V part) |
| Lead-Free | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] | — |
| Device System Gates | — | 2500 |
| Number of Macro Cells | — | 128 |
| Number of User I/Os | — | 68 |
| Number of Logic Blocks/Elements | — | 8 |
| Number of Global Clocks | — | 2 |
| Product Terms per Macro Cell | — | 32 |
| Maximum Operating Frequency | — | 147.1 MHz |
| Pin-to-Pin Delay (Speed Grade) | — | 6 ns |
| Tensión de alimentación | — | 5 V |
| Program Memory Type | — | EEPROM |
| In-System Programmability | — | Yes (ISP via JTAG) |