EPM7128SQC100-10 vs EPM7128SQC100-10N Comparación
Comparación detallada lado a lado de EPM7128SQC100-10 por Altera y EPM7128SQC100-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7128SQC100-10 | EPM7128SQC100-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $14,95 |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | 128 |
| Logic Elements / Gates | 2,500 usable gates | — |
| Maximum User I/O | 84 | — |
| Logic Array Blocks (LABs) | 16 | 8 (16 macro cells each) |
| Maximum Operating Frequency | 100 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Tensión de alimentación | 5 V | — |
| Process Technology | 5V CMOS, EEPROM-based | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Encapsulado | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (BQFP) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: rohs_status] | — |
| Usable Gates | — | 2,500 |
| User I/O Pins | — | 84 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V (4.75 V to 5.25 V) |
| I/O Voltage Tolerance | — | 3.3 V or 5 V (MultiVolt interface) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE Std 1149.1), 4-pin |
| Lead-Free / RoHS Status | — | Lead-free (N suffix) |
| Architecture Generation | — | Second-generation MAX |