EPM7128SQC100-15 vs EPM7128STC100-15N Comparación
Comparación detallada lado a lado de EPM7128SQC100-15 por Altera y EPM7128STC100-15N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
EPM7128SQC100-15 ⚠ Última compraIntel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteComparación de especificaciones
| Parámetro | EPM7128SQC100-15 | EPM7128STC100-15N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $8,20 | $9,20 |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 4 (16 macrocells each) | 8 (16 macro cells each) |
| User I/Os | 84 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX value] | — |
| Typical Gate Count | 2,500 gates | — |
| Supply Voltage (VCCINT) | 5 V (5% tolerance) | — |
| Programming Technology | EEPROM (in-system programmable via JTAG) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| Encapsulado | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin TQFP |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Tipo de montaje | Surface Mount | — |
| Nivel MSL | 3 (168 hours) | — |
| Estado RoHS | Non-compliant (SnPb lead finish - legacy PQFP) | Non-RoHS (legacy SnPb finish typical) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2,500 |
| Macro Cells | — | 128 |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns (-15 speed grade) |
| Maximum Internal Frequency | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (VCCIO) | — | 3.3 V or 5 V (per bank) |
| Technology | — | CMOS EEPROM, in-system programmable |
| JTAG (IEEE 1149.1) | — | Yes - in-system programming |
| Output Options | — | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | — | 4 global inputs |
| Estado del ciclo de vida | — | Obsolete (PDN effective 2017-06-01) |