EPM7128SQC100-7F vs EPM7128SQC100-15 Comparación
Comparación detallada lado a lado de EPM7128SQC100-7F por Altera y EPM7128SQC100-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
EPM7128SQC100-15 ⚠ Última compraComparación de especificaciones
| Parámetro | EPM7128SQC100-7F | EPM7128SQC100-15 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $8,20 |
| Family | MAX 7000S | MAX 7000 |
| Logic Elements / Blocks | 8 LABs | — |
| Number of Macrocells | 128 | — |
| Number of Usable Gates | 2,500 | — |
| Maximum Operating Frequency | 125 MHz | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 15 ns |
| Number of User I/O | 84 | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 5 V (5% tolerance) |
| Programmable Type | In-System Programmable (ISP), EEPROM | — |
| JTAG Boundary-Scan | Yes (IEEE 1149.1 BST) | — |
| Open-Drain Output Option | Yes | — |
| Temperatura de funcionamiento | 0 °C to 70 °C (Commercial) | 0C to +70C (Commercial) |
| Encapsulado | 100-pin PQFP (SQC100), surface-mount | 100-pin PQFP (Plastic Quad Flat Pack) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Lead-Free (Pb-Free) | Yes (matte-tin, '-F' suffix) | — |
| Estado RoHS | [DATA_NEEDED: confirmed from manufacturer] | Non-compliant (SnPb lead finish - legacy PQFP) |
| Tipo de memoria | Non-volatile (EEPROM configuration) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells each) |
| User I/Os | — | 84 |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX value] |
| Typical Gate Count | — | 2,500 gates |
| Programming Technology | — | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Nivel MSL | — | 3 (168 hours) |