EPM7128SQC160-15 vs EPM7128SQC160-6 Comparación
Comparación detallada lado a lado de EPM7128SQC160-15 por Intel y EPM7128SQC160-6 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128SQC160-6 - MAX 7000S 128-Macro Cell CPLD, 6ns, PQFP-160 | Altera/Intel
EPM7128SQC160-6 ObsoleteComparación de especificaciones
| Parámetro | EPM7128SQC160-15 | EPM7128SQC160-6 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $11,10 |
| Series | MAX 7000 | MAX 7000S |
| Programmable Type | In-System Programmable (EEPROM) | In-System Programmable (ISP) via JTAG |
| Number of Macrocells | 128 | — |
| Number of Logic Elements/Blocks | 8 (LABs of 16 macrocells each) | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O | 100 | — |
| Propagation Delay (tpd) | 15 ns max | — |
| Logic Element Propagation Delay | 4.5 ns | — |
| Maximum Operating Frequency | 125 MHz (internal feedback) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Logic Family | CMOS | — |
| Temperatura de funcionamiento | 0C to +70C (commercial grade) | — |
| Encapsulado / Carcasa | 160-BQFP (160-PQFP, 28x28 mm) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Configuration Memory | EEPROM (non-volatile, ~100 erase/program cycles) | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status — Altera MAX 7000S family was originally lead-based; lead-free variants exist with -N suffix] |
| Product Status | Obsolete (per distributor listings) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 128 |
| Usable Gates | — | 2500 |
| User I/O Pins | — | 100 |
| Logic Array Blocks (LABs) | — | 4 |
| Pin-to-Pin Propagation Delay (tPD) | — | 6 ns |
| Maximum Internal Frequency (fMAX) | — | 147.1 MHz |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | — | 0.5 µm CMOS EEPROM |
| Operating Temperature (Commercial) | — | 0 °C to +70 °C |
| Encapsulado | — | 160-Pin PQFP (28 × 28 mm) |
| Supplier Device Package | — | 160-PQFP (28×28) |
| JTAG Support | — | Yes (IEEE Std 1149.1) |
| Nivel MSL | — | [DATA_NEEDED: MSL rating not in verified data] |