EPM7128STC100-15N vs EPM7128STC100-6N Comparación
Comparación detallada lado a lado de EPM7128STC100-15N por Intel y EPM7128STC100-6N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteAltera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteComparación de especificaciones
| Parámetro | EPM7128STC100-15N | EPM7128STC100-6N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,20 | $10,50 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| Maximum User I/O | 84 | — |
| Pin-to-Pin Logic Delay (tPD) | 15 ns (-15 speed grade) | — |
| Maximum Internal Frequency | 76.9 MHz | 147.1 MHz |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Supply Voltage (VCCIO) | 3.3 V or 5 V (per bank) | 5 V |
| Technology | CMOS EEPROM, in-system programmable | — |
| Encapsulado | 100-pin TQFP | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| JTAG (IEEE 1149.1) | Yes - in-system programming | — |
| Output Options | Totem-pole or open-drain (per pin) | — |
| Dedicated Inputs | 4 global inputs | — |
| Estado RoHS | Non-RoHS (legacy SnPb finish typical) | Non-Compliant (lead-bearing package) |
| Estado del ciclo de vida | Obsolete (PDN effective 2017-06-01) | — |
| User I/Os | — | 84 |
| Logic Family | — | CMOS |
| Número de pines | — | 100 |
| Package Type | — | TQFP-100 |
| Internal Counter Frequency | — | 250 MHz |
| Propagation Delay (tPD) | — | 6 ns |
| Pin-to-Pin Delay | — | 4.5 ns |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| JTAG Support | — | IEEE 1149.1 Boundary Scan |
| Tipo de montaje | — | Surface Mount |