EPM7128STC100-6N vs EPM7128SQC100-7N Comparación
Comparación detallada lado a lado de EPM7128STC100-6N por Altera y EPM7128SQC100-7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteIntel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N ObsoleteComparación de especificaciones
| Parámetro | EPM7128STC100-6N | EPM7128SQC100-7N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,50 | $7,10 |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | — |
| User I/Os | 84 | — |
| Logic Family | CMOS | — |
| Número de pines | 100 | — |
| Package Type | TQFP-100 | — |
| Maximum Internal Frequency | 147.1 MHz | — |
| Internal Counter Frequency | 250 MHz | — |
| Propagation Delay (tPD) | 6 ns | — |
| Pin-to-Pin Delay | 4.5 ns | — |
| Supply Voltage (VCCIO) | 5 V | — |
| Process Technology | CMOS EEPROM | 0.30 µm CMOS EEPROM |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | Non-Compliant (lead-bearing package) | Compliant (lead-free 'N' suffix) |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Program Memory Type | — | EEPROM |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks | — | 8 |
| Number of Global Clocks | — | 2 |
| Product Terms per Macrocell | — | 32 |
| System Gates | — | 5,000 (max) |
| Maximum User I/Os | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Counter Speed | — | 175.4 MHz |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Operating Voltage (Core) | — | 5.0 V |
| I/O Standard Support | — | multiVolt (2.5V, 3.3V, 5.0V) |
| Encapsulado | — | 100-pin PQFP (QFP-100) |
| Security Bit | — | Programmable (one per device) |