EPM7160ELC84-12 vs EPM7160SLC84-10N Comparación
Comparación detallada lado a lado de EPM7160ELC84-12 por Altera y EPM7160SLC84-10N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera
EPM7160ELC84-12 ⚠ Última compra
Comparación de especificaciones
| Parámetro | EPM7160ELC84-12 | EPM7160SLC84-10N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $11,10 | $9,85 |
| Manufacturer | Altera (Intel PSG) | — |
| Series | MAX 7000 (MAX 7000E) | — |
| Programmable Type | EE PLD (EEPROM) | — |
| Number of Macrocells | 160 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of Usable Gates | 3,200 | — |
| Number of I/O (max) | 68 | — |
| Number of I/O (per package) | 64 | — |
| Propagation Delay tpd(1) max | 12 ns | — |
| Counter Frequency (max) | 90.9 MHz | — |
| Voltage Supply - Internal | 4.75 V to 5.25 V (5 V nominal) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Encapsulado / Carcasa | 84-LCC (J-Lead) | — |
| Supplier Device Package | 84-PLCC (29.31 x 29.31 mm) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | — |
| Family | — | MAX 7000S |
| Logic Elements / Macrocells | — | 160 macrocells |
| Usable Gates | — | 3,200 gates |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 64 (also reported as 60 or 36 depending on variant) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Counter Speed (fCNT) | — | up to 175.4 MHz |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage - Core (VCC) | — | 5.0 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programming | — | Yes, via IEEE Std. 1149.1 JTAG |
| Program / Erase Cycles | — | 100 minimum |
| Data Retention | — | 20 years minimum |
| Encapsulado | — | 84-pin PLCC (J-lead, surface mount) |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| Lead-Free / RoHS | — | Yes (-N suffix indicates lead-free) |