EPM7160ELC84-15 vs EPM7160ELC84-20 Comparación
Comparación detallada lado a lado de EPM7160ELC84-15 por Intel y EPM7160ELC84-20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7160ELC84-15 | EPM7160ELC84-20 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,95 | $16,95 |
| Family | MAX 7000 | MAX 7000 |
| Product Type | CPLD - Complex Programmable Logic Device | — |
| Architecture | EEPROM-based, second-generation MAX | Second-generation MAX |
| Usable Gates | 3,200 | 3,200 |
| Macrocells | 160 | 160 |
| Logic Array Blocks | 4 | 4 |
| Maximum I/O Pins | 36 | — |
| Pin-to-Pin Delay | 15 ns | — |
| Counter Frequency | 76.9 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Package Type | 84-pin PLCC (J-Lead) | — |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket compatible) |
| Temperatura de funcionamiento | 0 C to +70 C (commercial) | — |
| Estado RoHS | Contains lead / RoHS non-compliant (per Altera listing) | [DATA_NEEDED: RoHS compliance per specific part marking] |
| User I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Programming Interface | — | IEEE 1149.1 JTAG (ISP) |
| In-System Programmable | — | Yes (5.0-V ISP) |
| Encapsulado | — | PLCC-84 (windowed ceramic carrier not applicable - plastic) |
| Technology | — | CMOS EEPROM |
| Global Clock Inputs | — | 4 |
| Logic Element Type | — | EEPROM-based macrocell |