EPM7160SLC84-10 vs EPM7128SLC84-10 Comparación
Comparación detallada lado a lado de EPM7160SLC84-10 por Altera y EPM7128SLC84-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7160SLC84-10 | EPM7128SLC84-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $35,77 | $9,75 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | 128 |
| Logic Array Blocks (LABs) | 4 | — |
| Maximum User I/O Pins | 64 | — |
| Usable Gates | 3,200 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 5.0 V) | — |
| Technology | EEPROM-based CMOS | — |
| Encapsulado | 84-Pin PLCC (J-Lead) | PLCC-84 (J-lead) |
| Tipo de montaje | Surface Mount | Surface Mount (J-bend) |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| JTAG Boundary Scan | Yes (IEEE Std. 1149.1 compliant) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (contains lead in PLCC) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 2500 |
| User I/Os | — | 68 |
| Total Package Pins | — | 84 |
| Propagation Delay (tpd) | — | 10 ns |
| Internal Frequency | — | 250 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| MultiVolt I/O Support | — | 2.5 V / 3.3 V / 5 V |
| Program Memory Type | — | EEPROM (in-system programmable) |
| JTAG (IEEE 1149.1) | — | Yes |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |