EPM7160SLC84-10 vs EPM7160SLC84-6 Comparación
Comparación detallada lado a lado de EPM7160SLC84-10 por Altera y EPM7160SLC84-6 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7160SLC84-10 | EPM7160SLC84-6 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $35,77 | $15,86 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | 160 |
| Logic Array Blocks (LABs) | 4 | 4 (16 macrocells each) |
| Maximum User I/O Pins | 64 | — |
| Usable Gates | 3,200 | 3.2K |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 5.0 V) | Yes (5.0 V ISP via JTAG) |
| Technology | EEPROM-based CMOS | — |
| Encapsulado | 84-Pin PLCC (J-Lead) | 84-pin PLCC (29.31 x 29.31 mm) |
| Tipo de montaje | Surface Mount | Surface Mount (J-Lead) |
| Temperatura de funcionamiento | 0C to +70C (Commercial) | [DATA_NEEDED: commercial vs industrial grade] |
| JTAG Boundary Scan | Yes (IEEE Std. 1149.1 compliant) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Device Type | — | EE PLD (CPLD) |
| User I/O Pins | — | 36 (also reported as 64 depending on source) |
| Pin-to-Pin Delay (tPD) | — | 6 ns (speed grade -6) |
| Counter Frequency (fCNT) | — | 149.3 MHz |
| Tensión de alimentación | — | 4.75 V to 5.25 V (single 5 V supply) |
| Process Technology | — | CMOS EEPROM |
| JTAG Support | — | IEEE Std. 1149.1 compliant |
| MultiVolt I/O | — | Yes (mixed-voltage interface) |