EPM7192EGI160-20 vs EPM7192EQC160-20 Comparación
Comparación detallada lado a lado de EPM7192EGI160-20 por Intel y EPM7192EQC160-20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoleteComparación de especificaciones
| Parámetro | EPM7192EGI160-20 | EPM7192EQC160-20 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $264,10 | $58,26 |
| Family | MAX 7000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | — |
| Logic Array Blocks | 4 | — |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 4 | — |
| Pin-to-Pin Delay (tpd) | 20 ns | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (JTAG IEEE Std. 1149.1) | — |
| Encapsulado | 160-pin CPGA (Ceramic Pin Grid Array) | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status - non-RoHS era part] |
| Programming Interface | JTAG (ByteBlaster / USB-Blaster compatible) | — |
| Series | — | MAX 7000 |
| Programmable Type | — | EE PLD (EEPROM-based) |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of User I/O Pins | — | 124 (per package), 36 (per data source variant description) |
| Delay Time (tPD) | — | 20 ns |
| Internal Counter Frequency (fCNT) | — | 100 MHz typical |
| Temperatura de funcionamiento | — | -40C to +85C (industrial) |
| Encapsulado / Carcasa | — | 160-BQFP / 160-PQFP (28x28 mm) |
| Tipo de montaje | — | Surface Mount |
| In-System Programmable (ISP) | — | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) |
| Programmable Security Bit | — | Yes |
| Power-Saving Mode | — | Yes, programmable per macrocell |
| Nivel MSL | — | [DATA_NEEDED: MSL rating] |