EPM7192EGM160-15 vs EPM7192EGM160-20 Comparación
Comparación detallada lado a lado de EPM7192EGM160-15 por Altera y EPM7192EGM160-20 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoleteComparación de especificaciones
| Parámetro | EPM7192EGM160-15 | EPM7192EGM160-20 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $36,80 | $15,60 |
| Family | MAX 7000 | MAX 7000 |
| Sub-family | MAX 7000E | — |
| Device | EPM7192E | — |
| Macrocells | 192 | 192 |
| Usable Gates | 3750 | 600 to 5,000 |
| Logic Array Blocks (LABs) | 12 (16 macrocells each) | 12 |
| User I/O Pins | 124 | — |
| Encapsulado | 160-pin PGA (Pin Grid Array), ceramic | PGA-160 (160-pin Pin Grid Array) |
| Pin-to-Pin Logic Delay (tPD) | 15 ns | — |
| Supply Voltage (Core) | 5 V ±5% | — |
| I/O Voltage | 3.3 V or 5 V configurable | — |
| Technology | CMOS EEPROM (0.5 µm) | — |
| Programming Interface | JTAG (ByteBlaster / BitBlaster) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40C to +125C (industrial) |
| Tipo de montaje | Through-hole (PGA socket) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Type | — | EE CMOS CPLD (Electrically Erasable) |
| Maximum User I/O Pins | — | 120 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Pin-to-Pin Propagation Delay | — | 20 ns |
| Counter Frequency (max) | — | 175.4 MHz |
| I/O Standards | — | 3.3 V or 5 V configurable |
| Global Clock Inputs | — | 2 (GCLK1, GCLK2) |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Program/Erase Endurance | — | 100 cycles (EEPROM) |
| Technology Node | — | CMOS, second-generation MAX architecture |