EPM7192EQC160-20 vs EPM7192SQC160-10N Comparación
Comparación detallada lado a lado de EPM7192EQC160-20 por Intel y EPM7192SQC160-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7192EQC160-20 - 192-Macrocell MAX 7000 CPLD, 20ns, PQFP-160 | Intel
EPM7192EQC160-20 ObsoleteAltera
EPM7192SQC160-10N - 192-Macrocell MAX 7000S CPLD, 10ns, 160-Pin PQFP | Altera
EPM7192SQC160-10N NrndComparación de especificaciones
| Parámetro | EPM7192EQC160-20 | EPM7192SQC160-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $58,26 | $9,95 |
| Series | MAX 7000 | MAX 7000S |
| Programmable Type | EE PLD (EEPROM-based) | — |
| Number of Macrocells | 192 | — |
| Number of Logic Array Blocks | 4 | — |
| Number of User I/O Pins | 124 (per package), 36 (per data source variant description) | — |
| Delay Time (tPD) | 20 ns | — |
| Internal Counter Frequency (fCNT) | 100 MHz typical | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | 5.0 V |
| Temperatura de funcionamiento | -40C to +85C (industrial) | [DATA_NEEDED: commercial/industrial grade] |
| Encapsulado / Carcasa | 160-BQFP / 160-PQFP (28x28 mm) | 160-BQFP (PQFP, 0.65 mm pitch) |
| Tipo de montaje | Surface Mount | Surface Mount |
| In-System Programmable (ISP) | Yes, 5.0 V ISP via JTAG (IEEE Std. 1149.1) | — |
| Programmable Security Bit | Yes | — |
| Power-Saving Mode | Yes, programmable per macrocell | — |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Estado RoHS | [DATA_NEEDED: RoHS status - non-RoHS era part] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 7000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Usable Gates | — | 3,750 |
| User I/O Pins | — | 124 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |