EPM7256AEFC100-7 vs EPM7256AETC100-5C Comparación
Comparación detallada lado a lado de EPM7256AEFC100-7 por Intel y EPM7256AETC100-5C por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7256AETC100-5C - MAX 7000 CPLD, 256 Macrocells, 84 I/O, TQFP-100 | Altera
EPM7256AETC100-5C ObsoleteComparación de especificaciones
| Parámetro | EPM7256AEFC100-7 | EPM7256AETC100-5C |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,20 | $48,90 |
| Family | MAX 7000A | — |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 | — |
| Logic Array Blocks | 16 | — |
| User I/Os | 84 | — |
| Encapsulado | 100-pin FBGA (11x11 mm) | TQFP-100 |
| Recuento de pines | 100 | — |
| Supply Voltage - VCCINT | 3.0 V to 3.6 V | — |
| Supply Voltage - VCCIO | 2.5 V, 3.3 V, or 5 V (MultiVolt) | — |
| Propagation Delay (tPD) | 7.5 ns | 5 ns |
| Internal Toggle Rate | 250 MHz | — |
| Maximum Operating Frequency | 126.6 MHz | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Tipo de montaje | Surface Mount (FBGA) | Surface Mount |
| Temperatura de funcionamiento | 0C to +90C (commercial) | 0 °C to +70 °C (commercial) |
| Estado RoHS | [DATA_NEEDED: rohs status] | Non-compliant (Pb-bearing TQFP package) |
| Nivel MSL | [DATA_NEEDED: msl level] | — |
| Product Family | — | MAX 7000A |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O | — | 84 |
| Usable Gates (typical) | — | 6400 |
| Maximum Counter Frequency (fCNT) | — | 200 MHz |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5.0 V compatible |
| Programming Technology | — | EEPROM (in-system programmable via JTAG) |
| JTAG Support | — | IEEE Std. 1149.1 boundary-scan |
| Lead-Free | — | No |