EPM7256AEQC208-5N vs EPM7256AQI208-10 Comparación
Comparación detallada lado a lado de EPM7256AEQC208-5N por Altera y EPM7256AQI208-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7256AEQC208-5N | EPM7256AQI208-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $11,50 | $13,22 |
| Family | MAX 7000A | MAX 7000A |
| Logic Family / Base Technology | CMOS, EEPROM-based | — |
| Usable Gates | 5,000 | 5,000 |
| Macrocells | 256 | 256 |
| User I/Os | 164 | — |
| Dedicated Inputs | 16 | — |
| Número de pines | 208 | — |
| Encapsulado | 208-pin PQFP (Plastic Quad Flat Pack) | PQFP-208 |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Maximum Internal Frequency | 172.4 MHz | 93.5 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 5.5 ns | — |
| Speed Grade | -5 | — |
| Temperatura de funcionamiento | 0 C to +70 C (Commercial) | -40C to +85C (industrial) |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| Tipo de montaje | Surface Mount | — |
| Estado RoHS | unknown | Compliant (lead-free per distributor data) |
| Nivel MSL | [DATA_NEEDED: MSL Level] | — |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 68 |
| Pin-to-Pin Propagation Delay | — | 10 ns |
| Maximum Counter Frequency | — | 227.3 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Logic Compatibility | — | 5.0 V, 3.3 V, 2.5 V (MultiVolt) |
| Programmability | — | EEPROM, in-system via JTAG (IEEE 1149.1) |
| Process Technology | — | CMOS, EEPROM-based |