EPM7256AEQC208-5N vs EPM7256SQC208-10 Comparación
Comparación detallada lado a lado de EPM7256AEQC208-5N por Altera y EPM7256SQC208-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM7256SQC208-10 - MAX 7000S CPLD, 256 Macrocells, 10ns, 208-PQFP | Intel
EPM7256SQC208-10 ObsoleteComparación de especificaciones
| Parámetro | EPM7256AEQC208-5N | EPM7256SQC208-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $11,50 | $11,20 |
| Family | MAX 7000A | — |
| Logic Family / Base Technology | CMOS, EEPROM-based | — |
| Usable Gates | 5,000 | 5,000 |
| Macrocells | 256 | 256 |
| User I/Os | 164 | — |
| Dedicated Inputs | 16 | — |
| Número de pines | 208 | — |
| Encapsulado | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP (SQC208) |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Maximum Internal Frequency | 172.4 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 5.5 ns | — |
| Speed Grade | -5 | — |
| Temperatura de funcionamiento | 0 C to +70 C (Commercial) | 0C to +70C (commercial) |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS compliance status] |
| Nivel MSL | [DATA_NEEDED: MSL Level] | 3 (168 hours) |
| Series | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 16 |
| Number of I/O Pins | — | 164 |
| Propagation Delay (tPD) | — | 10 ns |
| Counter Speed (fCNT) | — | Up to 175.4 MHz |
| Programmable Technology | — | EEPROM (in-system programmable) |
| JTAG Support (IEEE 1149.1) | — | Yes |
| PCI Compliance | — | PCI Local Bus Specification 2.2 compliant |