EPM7256AETC100-5C vs EPM7256AETC100-5N Comparación
Comparación detallada lado a lado de EPM7256AETC100-5C por Altera y EPM7256AETC100-5N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7256AETC100-5C - MAX 7000 CPLD, 256 Macrocells, 84 I/O, TQFP-100 | Altera
EPM7256AETC100-5C ObsoleteComparación de especificaciones
| Parámetro | EPM7256AETC100-5C | EPM7256AETC100-5N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $48,90 | $9,75 |
| Product Family | MAX 7000A | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 256 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O | 84 | — |
| Usable Gates (typical) | 6400 | — |
| Propagation Delay (tPD) | 5 ns | — |
| Maximum Counter Frequency (fCNT) | 200 MHz | — |
| Encapsulado | TQFP-100 | TQFP-100 (1.0 mm pitch, 14x14 mm) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 3.3 V |
| I/O Voltage (MultiVolt) | 2.5 V / 3.3 V / 5.0 V compatible | — |
| Programming Technology | EEPROM (in-system programmable via JTAG) | — |
| JTAG Support | IEEE Std. 1149.1 boundary-scan | — |
| Temperatura de funcionamiento | 0 °C to +70 °C (commercial) | 0C to +70C (Commercial) |
| Estado RoHS | Non-compliant (Pb-bearing TQFP package) | Compliant (lead-free) |
| Lead-Free | No | — |
| Family | — | MAX 7000A |
| Series | — | MAX 7000AE |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 256 |
| Usable Gates | — | 5000 (range 600 to 10000) |
| User I/Os | — | 84 |
| Pin-to-Pin Delay (tPD) | — | 5.0 ns |
| Counter Frequency (fCNT) | — | up to 227.3 MHz |
| MultiVolt I/O Support | — | 2.5 V / 3.3 V / 5.0 V |
| Program Memory | — | Internal EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Nivel MSL | — | 3 (168 hours) |
| Process Technology | — | CMOS, EEPROM-based |
| Security Bit | — | Programmable |