EPM7256AETI144-7N vs EPM7256ATI144-10N Comparación
Comparación detallada lado a lado de EPM7256AETI144-7N por Intel y EPM7256ATI144-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7256ATI144-10N - 256-Macrocell MAX 7000A CPLD, 144-TQFP | Altera
EPM7256ATI144-10N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM7256AETI144-7N | EPM7256ATI144-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $29,81 | $30,10 |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 5000 | 5,000 |
| Macrocells | 256 | 256 |
| User I/Os | 36 (industrial variant) | — |
| Logic Elements | 256 | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V tolerant | — |
| Pin-to-Pin Logic Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fCNT) | 126.6 MHz | — |
| Process Technology | EEPROM (0.3 µm CMOS) | — |
| Encapsulado | TQFP-144 | TQFP-144 |
| Tipo de montaje | Surface Mount | — |
| Temperatura de funcionamiento | -40 °C to +85 °C (industrial) | -40C to +85C (industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / ByteBlaster | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance per datasheet] |
| Lead-Free | Yes (per Altera product page) | — |
| Nivel MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | [DATA_NEEDED: I/O count for 144-pin TQFP variant] |
| Pin-to-Pin Delay | — | 10 ns |
| Maximum Internal Frequency | — | 93.5 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| MultiVolt I/O Voltage VCCIO | — | 2.5 V or 3.3 V |
| Programming Method | — | IEEE Std. 1149.1 JTAG (ISP) |
| Non-volatile Configuration | — | Yes (EEPROM) |