EPM7256BQC208-7 vs EPM7256SQC208-15 Comparación
Comparación detallada lado a lado de EPM7256BQC208-7 por Intel y EPM7256SQC208-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM7256BQC208-7 | EPM7256SQC208-15 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,75 | $3,65 |
| Family | MAX 7000B | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 5,000 | 5000 |
| Macro Cells | 256 | — |
| User I/Os | 164 | — |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Maximum Internal Frequency | 126.6 MHz | — |
| Propagation Delay (tPD) | 7.5 ns (-7 speed grade) | — |
| Core Supply Voltage | 2.5 V | — |
| Temperatura de funcionamiento | 0C to +90C (commercial) | — |
| Encapsulado | 208-pin PQFP | 208-pin PQFP (28x28 mm) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Configuration Memory | Non-volatile EEPROM | EEPROM (non-volatile) |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| In-System Programmability | Yes (via JTAG) | — |
| Estado RoHS | Compliant per distributor listings | Contains lead / RoHS non-compliant (per third-party listing) |
| Series | — | EPM7256 |
| Macrocells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 164 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| Rango de temperatura de funcionamiento | — | 0 C to +70 C (Commercial) |
| Programmable Power Mode | — | Yes (per-macrocell turbo-bit) |
| JTAG (IEEE 1149.1) Boundary-Scan | — | Yes |
| In-System Programmability (ISP) | — | Yes |
| Lead-Free Status | — | Contains lead |