EPM9320ALC84-20 vs EPM9320ALC84-10N Comparación
Comparación detallada lado a lado de EPM9320ALC84-20 por Altera y EPM9320ALC84-10N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320ALC84-20 | EPM9320ALC84-10N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,50 | $21,40 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Encapsulado | PLCC-84 | 84-Pin PLCC (Plastic Leaded Chip Carrier) |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| Tensión de alimentación | 5.0 V | — |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Temperatura de funcionamiento | [DATA_NEEDED: commercial or industrial grade] | — |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | Through-Hole / Socket |
| Configuration Memory | Non-volatile EEPROM | — |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| Estado RoHS | [DATA_NEEDED: per Altera datasheet] | — |
| Series | — | MAX 9000A |
| Number of Macrocells | — | 320 |
| Number of Gates | — | 6,000 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 60 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency (fCNT) | — | 144.9 MHz |
| Supply Voltage (VCC) | — | 5.0 V nominal |
| Rango de temperatura de funcionamiento | — | 0C to +70C (Commercial) |
| Programmable Technology | — | EEPROM (in-system programmable) |
| Programming Interface | — | JTAG (IEEE 1149.1) |
| Part Status | — | Obsolete |