EPM9320ARC208-10 vs EPM9320ALC84-10 Comparación
Comparación detallada lado a lado de EPM9320ARC208-10 por Altera y EPM9320ALC84-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320ARC208-10 | EPM9320ALC84-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,40 | $19,80 |
| Device Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Maximum Frequency | 144.9 MHz | — |
| Tensión de alimentación | 5.0 V | — |
| Logic Blocks (LABs) | 16 | — |
| Programmability | EEPROM, in-system programmable via JTAG | — |
| JTAG Support | IEEE Std. 1149.1 compliant | — |
| Speed/Power Optimization | Per-macrocell programmable, 50% power mode available | — |
| Encapsulado | RQFP-208 (Power Quad Flat Pack) | 84-pin PLCC (J-Lead) |
| Tipo de montaje | Surface Mount | Surface Mount / Through-Hole (PLCC socket) |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: commercial/industrial grade] |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED] |
| Family | — | MAX 9000 |
| Device | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 52 |
| Dedicated Inputs | — | 16 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| Supply Voltage (VCCINT) | — | 5.0 V |
| In-System Programmability | — | 5.0 V ISP via IEEE 1149.1 JTAG |
| Technology | — | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Non-Volatile Configuration | — | Yes (EEPROM cell, powers up in known state) |
| Architecture | — | MAX (Multiple Array MatriX) with FastTrack Interconnect |