EPM9320GC280-15 vs EPM9320LC84-15 Comparación
Comparación detallada lado a lado de EPM9320GC280-15 por Altera y EPM9320LC84-15 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 Obsolete
Comparación de especificaciones
| Parámetro | EPM9320GC280-15 | EPM9320LC84-15 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $92,50 | $17,95 |
| Family | MAX 9000 (EPM9320) | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based, Multiple Array MatriX (MAX) | — |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 (16 macrocells per LAB) | 20 |
| Pin-to-Pin Propagation Delay | 15 ns | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Maximum User I/O Pins | 164 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5.0 V nominal) |
| I/O Voltage Levels | 3.3 V or 5 V (configurable) | — |
| Programmability | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG | 5.0 V in-system programmable (ISP) via JTAG |
| Encapsulado | 280-pin Ceramic Pin Grid Array (CPGA-280) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Tipo de montaje | Through-hole (PGA socket) | Surface Mount |
| Temperatura de funcionamiento | 0 C to +70 C (commercial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Nivel MSL | 3 (168 hours) | — |
| Estado RoHS | ROHS3 compliant (per fpgalink listing) | [DATA_NEEDED: confirm from manufacturer] |
| Technology Node | CMOS EEPROM, third-generation MAX | — |
| Series | — | EPM9320 |
| Propagation Delay (tPD) | — | 15 ns (max) |
| Frecuencia de reloj máxima | — | 117.6 MHz |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |