EPM9320LC84-15 vs EPM9320LI84-20N Comparación
Comparación detallada lado a lado de EPM9320LC84-15 por Intel y EPM9320LI84-20N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320LC84-15 | EPM9320LI84-20N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,95 | $9,75 |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 | 6,000 to 12,000 |
| Logic Array Blocks (LABs) | 20 | — |
| Propagation Delay (tPD) | 15 ns (max) | 20 ns (speed grade -20) |
| Frecuencia de reloj máxima | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| Encapsulado | 84-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Tipo de montaje | Surface Mount | — |
| Temperatura de funcionamiento | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0 C to +70 C (commercial) |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| Estado RoHS | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED: RoHS compliance status] |
| User I/O Pins | — | 60 |
| Total Pins | — | 84 |
| Pin-to-Pin Delay | — | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | — | 118 MHz |
| Logic Family | — | CMOS, EEPROM-based |
| Tensión de alimentación | — | 5.0 V |
| Programming Interface | — | IEEE 1149.1 JTAG, in-system programmable |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| Process Technology | — | Advanced CMOS EEPROM |