EPM9320LC84-15 vs EPM9400LC84-15 Comparación
Comparación detallada lado a lado de EPM9320LC84-15 por Intel y EPM9400LC84-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320LC84-15 | EPM9400LC84-15 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,95 | $23,10 |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | — |
| Usable Gates | 6,000 | 8,000 |
| Logic Array Blocks (LABs) | 20 | — |
| Propagation Delay (tPD) | 15 ns (max) | — |
| Frecuencia de reloj máxima | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | IEEE Std. 1149.1 compliant (ISP) |
| Encapsulado | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | 0C to +70C (Commercial) |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| Estado RoHS | [DATA_NEEDED: confirm from manufacturer] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 400 |
| Logic Array Blocks | — | 25 |
| Maximum User I/Os | — | 59 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Speed Grade | — | -15 (15 ns pin-to-pin delay) |
| Core Supply Voltage (VCCINT) | — | 5.0 V |
| Input Logic Compatibility | — | TTL, 3.3 V and 5.0 V tolerant |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| Minimum VCCINT | — | 4.75 V |
| Programming Method | — | In-System Programmable via JTAG |