EPM9320RC208-20 vs EPM9320ARC208-10N Comparación
Comparación detallada lado a lado de EPM9320RC208-20 por Altera y EPM9320ARC208-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9320RC208-20 | EPM9320ARC208-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,90 | $19,45 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | 20 | 16 |
| Usable Gates | 6,000 | — |
| Maximum I/O Pins | 132 | — |
| Propagation Delay (tPD max) | 20 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Programming Technology | EEPROM, in-system programmable (ISP) | — |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) | — |
| Temperatura de funcionamiento | 0 °C to 70 °C (commercial) | 0C to +70C (Commercial) |
| Encapsulado | 208-RQFP, exposed pad (208-BFQFP) | 208-pin RQFP (BFQFP with exposed pad) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 3rd generation | — |
| Process Technology | CMOS, 5.0 V EEPROM | — |
| Reprogrammability | Yes, unlimited ISP cycles | — |
| Macro Cells | — | 320 |
| Logic Gates | — | 6,000 gates |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency | — | 144.9 MHz |
| Supply Voltage (VCC) | — | 5 V |
| User I/O Pins | — | 168 |
| Dedicated Input Pins | — | 12 |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |
| Configuration Memory | — | Non-volatile EEPROM |
| Estado RoHS | — | Compliant (lead-free 'N' suffix) |