EPM9400LC84-20 vs EPM9320LC84-10 Comparación
Comparación detallada lado a lado de EPM9400LC84-20 por Altera y EPM9320LC84-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9400LC84-20 | EPM9320LC84-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $38,50 | $84,96 |
| Family | MAX 9000 | MAX 9000 EPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Architecture | Multiple Array Matrix (MAX), 3rd generation, EEPROM-based | — |
| Macrocells | 400 | 320 |
| Usable Gates | 8,000 (6,000 to 12,000 typical range) | 6000 (typical) |
| Flip-Flops | 580 | — |
| Maximum User I/O | 55 | — |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (configurable) | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Encapsulado | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (JEDEC MO-047) |
| Process Technology | CMOS EEPROM | 0.7 µm CMOS EEPROM/UV-EPROM |
| Temperatura de funcionamiento | Commercial (0C to +70C) - assumed from -20 speed grade | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] |
| Tipo de montaje | Surface Mount (PLCC socket or SMT land pattern) | Surface Mount (PLCC socket also common) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink listing) |
| Device | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | [DATA_NEEDED: fCNT in MHz] |
| Supply Voltage (VCC) | — | 5.0 V (typical, see datasheet) |
| Programming Interface | — | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Configuration | — | Non-volatile EEPROM (instant-on, no boot PROM) |
| Nivel de sensibilidad a la humedad (MSL) | — | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | — | 1-7 days (per fpgalink listing) |