EPM9480RC208-15 vs EPM9560ARI208-10N Comparación
Comparación detallada lado a lado de EPM9480RC208-15 por Intel y EPM9560ARI208-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
EPM9560ARI208-10N ObsoleteComparación de especificaciones
| Parámetro | EPM9480RC208-15 | EPM9560ARI208-10N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $24,95 | $22,10 |
| Family | MAX 9000 | MAX 9000 |
| Logic Cells / Macro Cells | 480 macro cells | — |
| Usable Gates | 10,000 gates | 12,000 |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tPD) | 15 ns | — |
| User I/O Pins | 153 | — |
| Tensión de alimentación | 5.0 V | 5.0 V |
| Programmability | In-System (ISP) via JTAG IEEE 1149.1 | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Encapsulado | RQFP-208 | 208-pin RQFP (Plastic) |
| Temperatura de funcionamiento | -40C to +85C (commercial) | 0 C to 70 C (Commercial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Nivel MSL | [DATA_NEEDED: MSL rating] | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum User I/O Pins | — | 212 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD1) | — | 10 ns |
| Clock-to-Output (tCO) | — | 4.5 ns |
| Setup Time (tSU) | — | 3.0 ns |
| Maximum Counter Frequency (fCNT) | — | 144.9 MHz |
| Logic Family | — | CMOS EEPROM |
| Programming Interface | — | JTAG (IEEE 1149.1) - In-System Programmable |