EPM9560ARI240-10 vs EPM9560ARC240-10N Comparación
Comparación detallada lado a lado de EPM9560ARI240-10 por Altera y EPM9560ARC240-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560ARC240-10N - MAX 9000 CPLD 560 Macro 191 IOs | Altera/Intel
EPM9560ARC240-10N ObsoleteComparación de especificaciones
| Parámetro | EPM9560ARI240-10 | EPM9560ARC240-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $19,50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | — |
| Macro Cells | 560 | 560 |
| User I/O Pins | 191 | — |
| Encapsulado | 240-pin RQFP (PowerQuad Flat Pack) | 240-pin RQFP (32x32 mm) |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Internal Frequency | 144.9 MHz | — |
| Tensión de alimentación | 5.0 V | — |
| Technology | CMOS, EEPROM-based configuration | — |
| Rango de temperatura de funcionamiento | -40 C to +85 C (industrial) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Logic Architecture | Multiple Array MatriX (MAX) with global interconnect array | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-RoHS (legacy Altera part) |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Number of Terminals | 240 | — |
| Terminal Form | Gull Wing | — |
| Logic Family | — | MAX 9000 (CPLD) |
| Process Technology | — | CMOS EEPROM |
| User I/Os | — | 191 |
| Logic Array Blocks (LABs) | — | 16 |
| Propagation Delay (tPD) | — | 10 ns |
| Internal Frequency (fMAX) | — | 145 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Temperatura de funcionamiento | — | 0°C to +70°C (Commercial) |
| Programming Interface | — | IEEE 1149.1 JTAG / ByteBlaster |
| Programmability | — | In-system, EEPROM-based (non-volatile) |
| I/O Standard | — | 5.0 V TTL-compatible |