EPM9560RC208-21 vs EPM9560RC208-20N Comparación
Comparación detallada lado a lado de EPM9560RC208-21 por Intel y EPM9560RC208-20N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM9560RC208-21 - MAX 9000 CPLD, 560 Macrocells, 208-Pin RQFP | Intel (Altera)
EPM9560RC208-21 ⚠ Última compraComparación de especificaciones
| Parámetro | EPM9560RC208-21 | EPM9560RC208-20N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $22,95 | $0,00 |
| Family | MAX 9000 | — |
| Architecture | Multiple Array MatriX (MAX), third-generation | — |
| Technology | CMOS EEPROM-based | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | 16 | — |
| Flip-Flops | 772 | 772 (per EPM9560 series data) |
| Maximum User I/O | 149 | — |
| Propagation Delay (speed grade -21) | 21 ns (max, per speed grade designation) | — |
| Tensión de alimentación | 5.0 V | 5.0 V |
| I/O Voltage Tolerance | 3.3 V or 5 V (per variant) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | Yes, via IEEE Std. 1149.1 JTAG |
| Encapsulado | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PowerQuad Flat Pack) |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial or commercial grade -21 suffix] | [DATA_NEEDED: operating temperature range] |
| Configuration Memory | EEPROM (non-volatile) | — |
| Security Bit | Yes (programmable) | — |
| Estado RoHS | [DATA_NEEDED: confirm RoHS compliance for -21 variant] | Lead-free (N suffix) |
| Device Family | — | MAX 9000 (EPM9560) |
| Propagation Delay (tPD) | — | 20 ns |
| User I/O Pins | — | 149 |
| Configuration Technology | — | EEPROM (non-volatile) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Tipo de montaje | — | Surface Mount |
| Logic Architecture | — | Multiple Array MatriX (MAX), third-generation CMOS EEPROM |
| Speed Grade | — | -20 (20 ns) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |