EPM9560RC240-20C vs EPM9560RI240-20N Comparación
Comparación detallada lado a lado de EPM9560RC240-20C por Altera y EPM9560RI240-20N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RC240-20C | EPM9560RI240-20N |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $195,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 12 |
| Maximum User I/O Pins | 216 | — |
| Pin-to-Pin Propagation Delay (tPD1) | 20 ns | — |
| Internal Counter Frequency (fCNT) | 144 MHz | — |
| Tensión de alimentación | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (5.0 V ISP) | — |
| Encapsulado | 240-pin RQFP (PowerQuad/RC) | 240-pin Power-enhanced BGA (RI240) |
| Temperatura de funcionamiento | 0 C to 70 C (commercial) | 0C to +70C (commercial) |
| Tipo de montaje | Surface Mount | — |
| Logic Family | CMOS | CMOS |
| Speed Grade | -20 (20 ns) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| User I/Os | — | 191 |
| Maximum Internal Frequency | — | 145 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 11.4 ns |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-system programmable (ISP) via JTAG (IEEE 1149.1) |
| Core Supply Voltage | — | 5.0 V |
| MultiVolt I/O | — | 5.0 V / 3.3 V compatible |
| Programming Language Support | — | AHDL, VHDL, Verilog HDL |
| Development Tools | — | MAX+PLUS II, Quartus II |