EPM9560RC304-15 vs EPM9560RC304-15F Comparación
Comparación detallada lado a lado de EPM9560RC304-15 por Altera y EPM9560RC304-15F por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoleteComparación de especificaciones
| Parámetro | EPM9560RC304-15 | EPM9560RC304-15F |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,40 | $18,75 |
| Device Family | MAX 9000 | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX), EEPROM-based | Multiple Array MatriX (MAX) with PIA interconnect |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | 16 (40 macrocells each) |
| User I/O Pins | 212 (maximum) | 212 |
| Propagation Delay (tPD) | 15 ns (combinatorial, pin-to-pin) | — |
| Recuento de pines | 304 | — |
| Encapsulado | 304-pin RQFP (Plastic Quad Flat Pack) | RQFP-304 (304-pin Plastic QFP) |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Standard | 5.0 V TTL / PCI-compliant | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Technology Node | High-performance CMOS, EEPROM process | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial temperature grade] | -40C to +85C (industrial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: lead-free / RoHS compliance status] | [DATA_NEEDED: rohs status - not stated in source] |
| Series | — | EPM9560 |
| Usable Gates | — | 12,000 |
| Propagation Delay (tpd) | — | 16.6 ns (max) |
| Maximum Internal Frequency | — | 117.6 MHz |
| Core Supply Voltage | — | 5.0 V |
| Dedicated Inputs | — | 4 |
| Programming Technology | — | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) |
| Boundary Scan Test (BST) | — | Yes, JTAG-compliant |
| Process Technology | — | High-performance CMOS, EEPROM-based |
| Nivel MSL | — | 3 (168 hours) |