EPM9560RC304-20 vs EPM9560RC304-15C Comparación
Comparación detallada lado a lado de EPM9560RC304-20 por Altera y EPM9560RC304-15C por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C ObsoleteComparación de especificaciones
| Parámetro | EPM9560RC304-20 | EPM9560RC304-15C |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $24,50 |
| Device Family | MAX 9000 (EPM9560) | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| User I/O Lines | 212 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Maximum Operating Frequency | 100 MHz | 117.6 MHz |
| Core Supply Voltage | 5.0 V | — |
| I/O Voltage | 3.3 V or 5 V (configurable) | — |
| Configuration Technology | EEPROM (in-system programmable) | — |
| JTAG Interface | IEEE Std. 1149.1 (built-in) | — |
| Encapsulado | 304-pin RQFP | 304-pin RQFP |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (Commercial) |
| Logic Array Blocks (LABs) | 20 | 16 |
| Speed Grade | -20 | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| Macro Cells | — | 560 |
| User I/O Pins (maximum) | — | 212 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Tensión de alimentación | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Program/Erase Endurance | — | 100 cycles minimum |