EPM9560RC304-20C vs EPM9560RC304-15C Comparación
Comparación detallada lado a lado de EPM9560RC304-20C por Altera y EPM9560RC304-15C por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560RC304-20C - MAX 9000 CPLD, 560 Macrocells, 5V | Intel / Altera
EPM9560RC304-20C ObsoleteAltera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C ObsoleteComparación de especificaciones
| Parámetro | EPM9560RC304-20C | EPM9560RC304-15C |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $162,00 | $24,50 |
| Family | MAX 9000 | MAX 9000 |
| Device Series | EPM9560 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 212 | — |
| fMAX (Internal) | 100 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns (speed grade -20) | — |
| Core Supply Voltage | 5.0 V | — |
| I/O Logic Level | 3.3 V or 5 V (configurable) | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Temperatura de funcionamiento | 0 C to +70 C (commercial) | 0 C to +70 C (Commercial) |
| Encapsulado | 304-pin RQFP | 304-pin RQFP |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| Macro Cells | — | 560 |
| User I/O Pins (maximum) | — | 212 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Tensión de alimentación | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Program/Erase Endurance | — | 100 cycles minimum |