EPM9560RC304-20N vs EPM9560RC304-15F Comparación
Comparación detallada lado a lado de EPM9560RC304-20N por Altera y EPM9560RC304-15F por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoleteComparación de especificaciones
| Parámetro | EPM9560RC304-20N | EPM9560RC304-15F |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $18,75 |
| Device Family | MAX 9000 (EPM9560) | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 20 | 16 (40 macrocells each) |
| User I/O Pins | 212 | 212 |
| Pin-to-Pin Propagation Delay | 20 ns (speed grade -20) | — |
| Maximum System Frequency | 100 MHz | — |
| Core Supply Voltage | 5.0 V | 5.0 V |
| I/O Voltage Support | 3.3 V or 5.0 V configurable | — |
| Configuration Technology | EEPROM (non-volatile, in-system programmable) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | — |
| Encapsulado | 304-pin RQFP (PowerQuad) | RQFP-304 (304-pin Plastic QFP) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | — |
| Estado RoHS | RoHS3 Compliant | [DATA_NEEDED: rohs status - not stated in source] |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Manufacturer Standard Lead Time | 1-7 Days (distributor listing) | — |
| Series | — | EPM9560 |
| Propagation Delay (tpd) | — | 16.6 ns (max) |
| Maximum Internal Frequency | — | 117.6 MHz |
| Dedicated Inputs | — | 4 |
| Programming Technology | — | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) |
| Architecture | — | Multiple Array MatriX (MAX) with PIA interconnect |
| Boundary Scan Test (BST) | — | Yes, JTAG-compliant |
| Temperatura de funcionamiento | — | -40C to +85C (industrial) |
| Process Technology | — | High-performance CMOS, EEPROM-based |
| Nivel MSL | — | 3 (168 hours) |