EPM9560RI208-10 vs EPM9560RI208-15N Comparación
Comparación detallada lado a lado de EPM9560RI208-10 por Intel y EPM9560RI208-15N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RI208-10 | EPM9560RI208-15N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $67,80 | $19,45 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 12,000 | — |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| User I/O Pins | 212 (typical for 208-RQFP package) | — |
| Encapsulado | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Ruggedized Quad Flat Pack) |
| Tipo de montaje | Surface Mount | — |
| Temperatura de funcionamiento | -40 °C to +85 °C (Industrial) | 0C to 70C (Commercial) |
| Programming Interface | IEEE 1149.1 (JTAG) / ISP | IEEE 1149.1 JTAG, 5.0-V in-system |
| Configuration Memory | EEPROM, 100 erase/program cycles | CMOS EEPROM, in-system programmable |
| Estado RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Lead Time | 1-7 days (per fpgalink listing) | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Device Family | — | MAX 9000 |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| Total Pins | — | 356 (per third-party catalog; see _validation_note) |
| Package Pin Count | — | 208 |
| Terminal Form | — | Gull Wing |
| Package Code | — | HFQFP |
| User I/Os | — | 216 (per DigiChip specification; see _validation_note) |
| Maximum Internal Frequency | — | 145 MHz |
| Propagation Delay (tPD) | — | 11.4 ns (15 ns speed grade) |
| Speed Grade | — | -15 |
| Tensión de alimentación | — | 5.0 V |
| Temperature Grade | — | Industrial (per Vyrian/Partstack listings) |
| Logic Family | — | CMOS |