EPM9560RI208-10 vs EPM9560RI208-20 Comparación
Comparación detallada lado a lado de EPM9560RI208-10 por Intel y EPM9560RI208-20 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RI208-10 | EPM9560RI208-20 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $67,80 | $21,10 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 16 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| User I/O Pins | 212 (typical for 208-RQFP package) | — |
| Encapsulado | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power-Quad Flat Pack) 28x28 mm |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | -40 °C to +85 °C (Industrial) | [DATA_NEEDED: operating temperature range grade] |
| Programming Interface | IEEE 1149.1 (JTAG) / ISP | — |
| Configuration Memory | EEPROM, 100 erase/program cycles | — |
| Estado RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS compliance status] |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 Hours) | — |
| Lead Time | 1-7 days (per fpgalink listing) | — |
| Architecture | — | Multiple Array MatriX (MAX) - third generation |
| Macro Cells | — | 560 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Propagation Delay (tPD) | — | 20 ns |
| Counter Frequency (fCNT) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |