EPM9560RI208-10N vs EPM9560RI208-10 Comparación
Comparación detallada lado a lado de EPM9560RI208-10N por Altera y EPM9560RI208-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RI208-10N | EPM9560RI208-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $61,75 | $67,80 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | — |
| Usable Gates | 12,000 | 12,000 |
| Macro Cells | 560 | — |
| Register Bits | 12,160 | — |
| User I/Os | 212 | — |
| Pin-to-Pin Delay | 10 ns (speed grade -10) | — |
| Maximum Frequency | 100 MHz to 125 MHz | — |
| Tensión de alimentación | 5 V | — |
| Encapsulado | 208-pin RQFP (PQFP) | 208-pin RQFP (Power Quad Flat Pack) |
| Temperatura de funcionamiento | -40C to +85C (Industrial grade, "RI" suffix) | -40 °C to +85 °C (Industrial) |
| Programming Method | In-system via IEEE 1149.1 (JTAG) | — |
| Nivel MSL | 3 (168 Hours) | — |
| Estado RoHS | ROHS3 Compliant (per fpgalink) | ROHS3 Compliant |
| Configuration Memory | On-chip EEPROM (non-volatile) | EEPROM, 100 erase/program cycles |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| User I/O Pins | — | 212 (typical for 208-RQFP package) |
| Tipo de montaje | — | Surface Mount |
| Programming Interface | — | IEEE 1149.1 (JTAG) / ISP |
| Nivel de sensibilidad a la humedad (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |