EPM9560RI208-15 vs EPM9560RI208-20N Comparación
Comparación detallada lado a lado de EPM9560RI208-15 por Intel y EPM9560RI208-20N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RI208-15 | EPM9560RI208-20N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $20,10 | $0,00 |
| Family | MAX 9000 | — |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | — |
| Macrocells | 560 | 560 |
| Typical Usable Gates | 12,000 | — |
| User I/Os | 153 | — |
| Internal Frequency (max) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade | — |
| Logic Family | CMOS | — |
| Número de pines | 208 | — |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) | — |
| Package Type | RQFP-208 | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O | — |
| Temperatura de funcionamiento | 0 °C to 70 °C (industrial grade; per package suffix R) | Industrial (-40C to +85C) |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | Yes, via IEEE Std. 1149.1 JTAG |
| Boundary-Scan (JTAG) | Compliant | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | — |
| Estado RoHS | ROHS3 Compliant | [DATA_NEEDED: RoHS status] |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 hours) | — |
| Device Family | — | MAX 9000 |
| Usable Gates | — | 12,000 |
| Pin-to-Pin Delay | — | 20 ns (-20 speed grade) |
| Counter Speed | — | 100 MHz |
| Tensión de alimentación | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| Encapsulado | — | 208-pin RQFP |
| Tipo de montaje | — | Surface Mount |
| Development Tool | — | MAX+PLUS II |
| Design Entry | — | Schematic, VHDL, Verilog HDL, AHDL |
| Packaging | — | Tray |
| Logic Architecture | — | Third-generation MAX (Multiple Array MatriX) |
| Fabrication Process | — | Advanced CMOS |