EPM9560RI208-15N vs EPM9560RI208-10N Comparación
Comparación detallada lado a lado de EPM9560RI208-15N por Altera y EPM9560RI208-10N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RI208-15N | EPM9560RI208-10N |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,45 | $61,75 |
| Manufacturer | Altera (Intel Programmable Solutions Group) | — |
| Device Family | MAX 9000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Configuration Memory | CMOS EEPROM, in-system programmable | On-chip EEPROM (non-volatile) |
| Encapsulado | 208-pin RQFP (Ruggedized Quad Flat Pack) | 208-pin RQFP (PQFP) |
| Total Pins | 356 (per third-party catalog; see _validation_note) | — |
| Package Pin Count | 208 | — |
| Terminal Form | Gull Wing | — |
| Package Code | HFQFP | — |
| User I/Os | 216 (per DigiChip specification; see _validation_note) | 212 |
| Maximum Internal Frequency | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (15 ns speed grade) | — |
| Speed Grade | -15 | — |
| Tensión de alimentación | 5.0 V | 5 V |
| Temperatura de funcionamiento | 0C to 70C (Commercial) | -40C to +85C (Industrial grade, "RI" suffix) |
| Temperature Grade | Industrial (per Vyrian/Partstack listings) | — |
| Logic Family | CMOS | — |
| Programming Interface | IEEE 1149.1 JTAG, 5.0-V in-system | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant (per fpgalink) |
| Family | — | MAX 9000 |
| Usable Gates | — | 12,000 |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| Nivel MSL | — | 3 (168 Hours) |