EPM9560RI208-20N vs EPM9560RI208-10 Comparación
Comparación detallada lado a lado de EPM9560RI208-20N por Intel y EPM9560RI208-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RI208-20N | EPM9560RI208-10 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $67,80 |
| Device Family | MAX 9000 | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Pin-to-Pin Delay | 20 ns (-20 speed grade) | — |
| Counter Speed | 100 MHz | — |
| Tensión de alimentación | 5.0 V | — |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| Encapsulado | 208-pin RQFP | 208-pin RQFP (Power Quad Flat Pack) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | Industrial (-40C to +85C) | -40 °C to +85 °C (Industrial) |
| Development Tool | MAX+PLUS II | — |
| Design Entry | Schematic, VHDL, Verilog HDL, AHDL | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Packaging | Tray | — |
| Logic Architecture | Third-generation MAX (Multiple Array MatriX) | — |
| Fabrication Process | Advanced CMOS | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 144 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| User I/O Pins | — | 212 (typical for 208-RQFP package) |
| Programming Interface | — | IEEE 1149.1 (JTAG) / ISP |
| Configuration Memory | — | EEPROM, 100 erase/program cycles |
| Nivel de sensibilidad a la humedad (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |