EPM9560RI240-15 vs EPM9560SRC240-15 Comparación
Comparación detallada lado a lado de EPM9560RI240-15 por Intel y EPM9560SRC240-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM9560RI240-15 - 560-Macrocell MAX 9000 CPLD, 15ns, RQFP-240 | Intel
EPM9560RI240-15 ObsoleteComparación de especificaciones
| Parámetro | EPM9560RI240-15 | EPM9560SRC240-15 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $23,10 | $22,50 |
| Product Type | EE PLD (Electrically Erasable Programmable Logic Device) | — |
| Family | MAX 9000 | MAX 9000 |
| Macrocells | 560 | 212 |
| Flip-Flops | 772 | — |
| User I/Os (industrial grade) | 191 | — |
| Dedicated Inputs | 4 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | — |
| Internal Frequency (max) | 145 MHz | — |
| Logic Family / Process | CMOS, EEPROM-based | — |
| Core Voltage | 5.0 V | — |
| I/O Voltage | 3.3 V or 5.0 V (configurable) | — |
| Architecture | Multiple Array MatriX (MAX), 3rd generation | — |
| Encapsulado | RQFP-240 (Power Quad Flat Pack, gull-wing, 0.500 mm pitch) | RQFP-240 (Surface Mount) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | -40 C to +85 C (industrial) | [DATA_NEEDED: commercial 0-70C or industrial -40-85C] |
| In-System Programmability | Yes, JTAG (IEEE Std 1149.1) | — |
| Power-Up Configuration | Instant-on (no external boot PROM) | — |
| I/O Undershoot Tolerance | -2.0 V for <20 ns (no-load) | — |
| I/O Overshoot Tolerance | 7.0 V for <20 ns (no-load) | — |
| Device Type | — | EPLD / CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 560 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | [DATA_NEEDED: exact I/O count for SRC240 package] |
| Speed Grade | — | -15 (15 ns tPD) |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns (max) |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Programmability | — | In-system programmable via IEEE 1149.1 JTAG |
| Non-volatile | — | Yes (EPROM/EEPROM cells) |
| Estado RoHS | — | [DATA_NEEDED: RoHS compliance not stated in provided data] |
| Process Technology | — | CMOS EPROM |