EPM9560RI304 vs EPM9560RC304-10 Comparación
Comparación detallada lado a lado de EPM9560RI304 por Altera y EPM9560RC304-10 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM9560RI304 | EPM9560RC304-10 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $17,60 |
| Device Family | MAX 9000 | — |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 16000 |
| Maximum User I/O Pins | 216 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 (JTAG) | — |
| Encapsulado | 304-pin BFQFP/RQFP (HFQFP) | RQFP-304 (RC) |
| Package Code | HFQFP, square | — |
| Terminal Form | Gull wing | — |
| Number of Terminals | 304 | — |
| Operating Temperature Grade | Industrial (-40C to +85C) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Architecture | Multiple Array MatriX (MAX) with Logic Array Blocks and Programmable Interconnect Array | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD / EPLD |
| Logic Elements | — | 560 |
| Recuento de pines | — | 304 |
| Pin-to-Pin Propagation Delay | — | 12 ns |
| Speed Grade | — | -10 |
| Tensión de alimentación | — | 5 V |
| Temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature range] |
| User I/O Pins | — | 304 (package-limited) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Programming Method | — | JTAG in-system (ISP) |
| Process Technology | — | 0.65 µm CMOS EEPROM |
| Nivel MSL | — | 3 (168 Hours) |