IRS21867STRPBF vs IR2110STRPBF Comparación
Comparación detallada lado a lado de IRS21867STRPBF por Infineon y IR2110STRPBF por Infineon. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | IRS21867STRPBF | IR2110STRPBF |
|---|---|---|
| Marca | Infineon | Infineon |
| Categoría | Power MOSFET Drivers | Power MOSFET Drivers |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1,55 | $1,35 |
| Topología | High-Side and Low-Side (Half-Bridge) | — |
| Offset Voltage (High-Side, max) | 600 V | 500 V |
| Output Current (Source/Sink, typical) | 4 A / 4 A | — |
| Supply Voltage VCC | 10 V to 20 V | — |
| Bootstrap Supply VBS | up to VCC + 600 V (floating) | — |
| Input Logic Compatibility | 3.3 V and 5 V CMOS / TTL | — |
| Rise Time (typ, 1 nF load) | 22 ns | — |
| Fall Time (typ, 1 nF load) | 18 ns | — |
| Turn-On Propagation Delay (typ) | 170 ns | — |
| Turn-Off Propagation Delay (typ) | 170 ns | — |
| Undervoltage Lockout | Yes (VCC and VBS) | — |
| Operating Temperature Range (TJ) | -40C to +150C | — |
| Encapsulado | 8-SOIC (SOIC-8, 8-pin SOIC N T/R) | 16-SOIC (SOIC W / 2110-S16) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | 2 | [DATA_NEEDED] |
| Estado RoHS | Compliant | Compliant (Pb-free, PBF suffix) |
| Lead-Free Status | Lead Free | — |
| Channel Count | 2 (1 high-side + 1 low-side) | — |
| Input Type | Non-Inverting (HIN, LIN) | — |
| Función | — | Half-Bridge Gate Driver |
| Number of Drivers | — | 2 (High-Side + Low-Side) |
| Driven Configuration | — | Half-Bridge |
| Channel Type | — | Independent, Synchronous |
| Tipo de salida | — | Non-Inverting |
| Peak Output Current (Source/Sink) | — | 2.5 A / 2.5 A |
| Supply Voltage (VCC) | — | 10 V to 20 V |
| Logic Input Compatibility | — | CMOS / LSTTL, down to 3.3 V logic |
| Input Threshold | — | Logic-level compatible (3.3 V / 5 V) |
| Undervoltage Lockout (UVLO) | — | Yes (both VCC and VBS) |
| Bootstrap Supply | — | Required for high-side channel |
| Rise Time (Typ) | — | 25 ns (at 1 nF load) [DATA_NEEDED: per-datasheet spec conditions] |
| Fall Time (Typ) | — | 17 ns (at 1 nF load) [DATA_NEEDED: per-datasheet spec conditions] |
| Propagation Delay (Typ) | — | [DATA_NEEDED: per-datasheet spec conditions] |
| Rango de temperatura de funcionamiento | — | -40 C to +125 C |
| Lead-Free | — | Yes (PBF suffix) |
| Qualification | — | [DATA_NEEDED: AEC-Q100 status] |