K3K9K90BM-MGCP vs K3LKBKB0BM-MGCP Comparación
Comparación detallada lado a lado de K3K9K90BM-MGCP por Samsung Electronics y K3LKBKB0BM-MGCP por Samsung Electronics. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Samsung Electronics
K3LKBKB0BM-MGCP - 32Gbit LPDDR5 DRAM 6400Mbps | Samsung
K3LKBKB0BM-MGCP ✓ ActivoComparación de especificaciones
| Parámetro | K3K9K90BM-MGCP | K3LKBKB0BM-MGCP |
|---|---|---|
| Marca | Samsung Electronics | Samsung Electronics |
| Categoría | Memory ICs | Memory ICs |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $47,15 | $46,62 |
| Tipo de memoria | LPDDR5 SDRAM (CMOS) | DRAM (LPDDR5 SDRAM) |
| Organización de memoria | [DATA_NEEDED: density and organization] | 1G x 32 |
| Pin Speed | Up to 6400 Mbps (family maximum per Samsung LPDDR5 page) | — |
| Interface Width | x32 (family standard for K3K/K3L BM packages) | — |
| Encapsulado | PBGA (Plastic Ball Grid Array) | FBGA-315 |
| Ball Count | [DATA_NEEDED: ball count] | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -25C to +85C |
| Supply Voltage (VDD) | [DATA_NEEDED: VDD voltage] | — |
| Refresh | Self-refresh with per-bank refresh support (LPDDR5 standard) | Self-refresh and auto-refresh (LPDDR5 standard) |
| Power Saving vs LPDDR4X | Approximately 20% (Samsung published figure) | — |
| Max Bandwidth | Up to 51.2 GB/s (family maximum per Samsung LPDDR5 page) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Moisture Sensitivity Level | [DATA_NEEDED: MSL level] | — |
| Clocking | WCK (word clock) architecture | — |
| Standards | JEDEC LPDDR5 | — |
| Tamaño de memoria | — | 32 Gbit |
| Velocidad de datos | — | 6400 Mbps per pin |
| Supply Voltage Rails | — | 500 mV, 900 mV, 1.05 V, 1.8 V |
| Interfaz | — | LPDDR5 x32 |
| Technology Generation | — | LPDDR5 (JEDEC LPDDR5 family) |
| Density per Package | — | 4 GB (32 Gbit) |
| Application Segment | — | Mobile, embedded, industrial computing |
| Standby / Deep Sleep | — | LPDDR5 deep-sleep power states |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |
| Access Time / Latency | — | [DATA_NEEDED: CAS latency] |