MC68HC000IEI16R vs MC68HC000CEI16 Comparación
Comparación detallada lado a lado de MC68HC000IEI16R por NXP Semiconductors y MC68HC000CEI16 por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
MC68HC000CEI16 - 32-Bit 16MHz M68k MPU, 68-PLCC | NXP / Motorola
MC68HC000CEI16 ✓ ActivoComparación de especificaciones
| Parámetro | MC68HC000IEI16R | MC68HC000CEI16 |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Obsolete | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $27,40 | $17,40 |
| Core Processor | EC000 (M68000 Family) | — |
| Number of Cores | 1 Core, 32-Bit | 1 |
| Speed / Clock Frequency | 16 MHz | — |
| Ancho del bus de datos | 16-bit external (32-bit internal registers) | — |
| Address Bus Width | 24-bit (16 MB address space) | — |
| Co-Processors / DSP | None | — |
| RAM Controllers | None (external memory required) | — |
| Graphics Acceleration | No | — |
| Display & Interface Controllers | None | — |
| Ethernet | None | — |
| SATA | None | — |
| USB | None | — |
| Voltage - I/O | 5.0 V | — |
| Encapsulado | 68-PLCC (24.21 mm x 24.21 mm) | 68-pin PLCC (J-Lead) 24.21 x 24.21 mm |
| Tipo de montaje | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket required) |
| Temperatura de funcionamiento | -40C to +85C (Industrial grade) | -40 C to +85 C (industrial) |
| Series | M680x0 | — |
| Part Status | Obsolete (last-time-buy may apply) | — |
| Estado RoHS | [DATA_NEEDED: rohs status] | — |
| Core Architecture | — | M68000 (M68k) - 32-bit CISC |
| Family Variant | — | EC000 (Enhanced CMOS, low power) |
| Frecuencia de reloj máxima | — | 16 MHz |
| External Data Bus Width | — | 16-bit (dynamic 8/16-bit sizing) |
| External Address Bus Width | — | 24-bit (16 MB address space) |
| Data Registers | — | 8 x 32-bit (D0-D7) |
| Address Registers | — | 8 x 32-bit (A0-A7, A7' supervisor stack) |
| Operating Modes | — | User and Supervisor (separate stack pointers) |
| Interrupt Levels | — | 7 (IPL0-IPL2 encoded, autovectored + vectored) |
| Tensión de alimentación | — | 3.3 V / 5 V tolerant |
| Lead Free / RoHS | — | Lead free, RoHS compliant |
| On-chip Clock Generator | — | Yes (external crystal or TTL clock at XTAL) |
| Typical Dhrystone Throughput | — | ~2 MIPS at 16 MHz |