P1010NXE5KHA vs P1010NXN5KHA Comparación
Comparación detallada lado a lado de P1010NXE5KHA por NXP Semiconductors y P1010NXN5KHA por NXP Semiconductors. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
NXP Semiconductors
P1010NXE5KHA - QorIQ P1010 1GHz e500v2 MPU 425-TEPBGA | NXP
P1010NXE5KHA ⚠ Última compraComparación de especificaciones
| Parámetro | P1010NXE5KHA | P1010NXN5KHA |
|---|---|---|
| Marca | NXP Semiconductors | NXP Semiconductors |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Última compra | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $52,10 | $25,95 |
| Manufacturer | NXP Semiconductors | — |
| Series | QorIQ P1 | — |
| Core | PowerPC e500v2 | — |
| Core Count | 1 | — |
| Ancho del bus de datos | 32-bit | — |
| Max Core Frequency | 1.0 GHz | — |
| L1 Cache (I/D per core) | 32 KB / 32 KB | — |
| L2 Cache | 256 KB (with ECC) | — |
| Temperatura de funcionamiento | -40C to +105C (extended) | -40C to +105C (Industrial / Extended) |
| Tensión de alimentación | 1.0 V core (typical) | 1.0 V core, 1.35 V / 1.5 V DDR3 I/O |
| Encapsulado | 425-TEPBGA I (19x19 mm) | 425-ball TEPBGA (Thermal Enhanced Plastic BGA) |
| Process Node | 45 nm | — |
| Security Engine | SEC 4.0 (AES, DES, Kasumi, SHA, PK) | SEC (crypto accelerator), Trusted Boot, Trust Architecture |
| Ethernet | 1x GbE MAC | 3x Gigabit Ethernet (eTSEC: 10/100/1000 + 2x RGMII) |
| PCIe | 2x PCIe Gen2 | 3x PCIe Gen 2.0 controllers |
| SATA | 2x SATA 2.0 | 2x SATA 2.0 interfaces |
| USB | USB 2.0 with ULPI | 2x USB 2.0 (host + device/host with ULPI) |
| Memory Controller | DDR3/DDR3L with ECC | DDR3 with ECC support, 16-bit interface |
| NAND Flash Controller | Yes (with ECC) | — |
| Trusted Boot | Yes (secure boot chain) | — |
| Estado RoHS | Compliant | Compliant |
| Nivel MSL | MSL3 (per JEDEC J-STD-020) | — |
| Core Architecture | — | Power Architecture e500v2, 32-bit, dual-issue |
| Core Frequency | — | 1000 MHz (1.0 GHz) |
| Instruction Set | — | Power Architecture, Book-E enhanced |
| Process Technology | — | 45 nm CMOS |
| L1 Cache (I/D) | — | 32 KB / 32 KB per core |
| Tipo de montaje | — | Surface Mount (BGA) |